Genlock Service Manual, PN-314983-01

—,

—— ee

SERVICE MANUAL

GENLOCK

“- commodore

COMPUTERS

SERVICE MANUAL

GENLOCK

JUNE, 1987 PN-314983-01

Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.

Commodore makes no expressed or implied war-
ranties with regard to the information contained
herein. The information is made available solely on
an as is basis, and the entire risk as to quality and
accuracy is with the user. Commodore shall not be
liable for any consequential or incidental damages
in connection with the use of the information con-
tained herein. The listing of any available replace-
ment part herein does not constitute in any case
a recommendation, warranty or guaranty as to
quality or suitability of such replacement part.
Reproduction or use without expressed permission,
of editorial or pictorial content, in any matter is
prohibited.

This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical,
photocopying, recording or otherwise, without the prior written permis-
sion of Commodore Electronics Limited.

Copyright © 1987 by Commodore Electronics Limited.
All rights reserved.

GENLOCK SERVICE MANUAL

GENLOCK — THEORY OF OPERATION

(In the following discussions the 74LS221 and 74LS123 with clock input pins 1 and 2 will be designated
by an A suffix and pins 9 and 10 by a B suffix. The 74LS74 with clock input pin 3 will be designated
by an A suffix and pin 11 by a B suffix.)

When the genlock is attached to the Amiga computer, the system clock for the computer comes from
the 28 MHz VCO in the genlock unit. During the power-up sequence the Kickstart configures the com-
puter into an external synch mode. The genlock unit extracts the horizontal and vertical timing informa-
tion from the external source video and resets the horizontal and vertical counters of the computer,
so that the computer video is synched to the external video. When the external video source is removed,
the computer is self-synchronized.

The genlock unit also allows for video overlay of the computer graphics over the source video and audio
mixing of the computer audio (or other source like microphone) with the audio of the source video. The
incoming composite video is decoded into RGB components, and the computer’s RGB is keyed in over
the external video RGB. The combined RGB signal then goes to the RGB output to drive an RGB monitor,
it also goes to a color encoder to drive a composite video monitor or a VCR.

The major system blocks of the genlock unit are: VCO and horizontal beam counter; synch separator
and detector; PLL; synch generator, color decoder timing generator, and horizontal and vertical reset
generator; color decoder and video overlay circuit; color encoder; and audio mixer circuit. Each section
is described in detail below. The section numbers correspond to the section numbers in the Trouble-
shooting Procedures.

VCO and Horizontal Counter

The VCO (voltage controlled oscillator) consists of CR7, Q13, Q12, and associated circuits. Q13 and
varactor, CR7, are the active elements of the 28.63636 MHz oscillator. The frequency changes approx-
imately +/- 1 MHz asthe VCO control voltage is varied —/+ 7 V around the 4.2 V nominal operating
point. The error voltage corresponds to the difference in phase between the horizontal synch of the
source video and the computer, so when they are in phase the oscillator is sitting at 28.63636 MHz.
The horizontal beam counter consists of divide-by-four prescaler, U16 and U25, and divide-by-455 counter,
U6, U10, U13, and U4. The RGH is the regenerated horizontal signal that mirrors the horizontal counter
of the computer in both phase and frequency. The 3.58 MHz clock from the computer is used to generate
the 7.16 MHz prescaler output, so that it would have a known time relation to the color clock of the
computer. This insures that the horizontal reset signal, which is derived from the RGH, has a proper
set-up and hold times when sampled by the computer's color clock.

Synch Separator and Detector

The source video synch separator consists of Q16, Q7, U3, and associated components. Q16 amplifies
the incoming 1 Vp-p signal six times. The diode bias circuit, CR3 and CR4, rolls off the white peak
of the video signal. The amplified signal then goes to the synch separator, U3, through a buffer, Q7.
The U3 is a comparator which slices the clamped synch signal at the voltage level set by R49. The
detected composite synch goes to rest of the board and to the external synch detector, U1B. If there
are more than 8 lines of external synch missing, the synch detector circuit switches the synch source
of the genlock to the computer, so that computer will self-synch.

Phase Locked Loop

The phased locked loop consists of VCO and horizontal counter, which were described previously, phase
comparator (consisting of ramp generator circuit, strobe generator circuit, sample-and-hold, and voltage
comparator), and integrator amplifier. The basic theory of the operation of the PLL is to convert the

GENLOCK SERVICE MANUAL

Theory of Operation (continued)

relative positions of the horizontal synch of the source video and RGH, which mirrors the horizontal
synch of the computer, to an error voltage to control the VCO. The RGH signal is used to generate
a ramp signal. The ramp generator circuit consists of U17A, U11B, and Q22. The U17A and U11B delays
the start of the ramp relative to the positive edge of RGH, so that when the PLL is locked the strobe
is sampling the proper portion of the ramp. The trimmers R133 and R162 allows for adjustment of the
delay to compensate for the tolerances of the one shot and ramp timing. The ramp circuit, Q22, charges
up quickly during the delay time, and discharge slowly after the delay time. The position and the dura-
tion of the ramp is chosen so that the strobe pulse, which occurs at the leading edge of the external
synch, is sampling the proper portion of the ramp when the PLL is locked. The strobe generator, U14
and Q21, generates a narrow strobe pulse at the leading edge of the source horizontal synch and samples
the ramp voltage. During off-time the voltage is pulled down to — 5 Vdc to cut off the JFET of the sample-
and-hold. The sampled voltage is held by Q25, C78, and U20. The sampled voltage is compared with
a reference voltage to give the phase error, and the error voltage is filtered and amplified before going
to the VCO. The phase-comparator consists of inputs to U20, pins 5 and 6. The reference voltage of
2 V is set by R156 and R157. When the PLL is locked both pins 5 and 6 will be at 2 V.

Synch, Video Decode Timing, and Reset Signals

The horizontal synch separator, U12B, triggers on the leading edge of the horizontal synch. The timing
is set for 48 usec to ignore the equalization pulses. The outputs of the U12 go to the field detect circuit
and U19A which recreates the 4.7 usec horizontal synch for the RGB connector. It also goes to the
strobe generator, described above, and the sandcastle generator.

The sandcastle generator consists of U2A, U7B, Q5 and Q6. U2A is triggered on the leading edge of
the source horizontal synch and times out the horizontal blanking interval. U7B is triggered on the trail-
ing edge of the source horizontal synch and times out the color burst gate interval. The output of the
two oneshots are summed and amplified by Q5 and Q6 to generate the 12 V two level signal to be used
by the color decoder.

The horizontal reset circuit consists of U17B and U14B. The reset signal occurs on the alternate cycle
of the horizontal beam counter. The FF U17B is toggled by the rising edge of RGH, and U14B is trig-
gered by the rising edge of the U17B output. A 32 usec reset pulse is sent to the computer at the begin-
ning of every other line.

The vertical synch separator consists of Q3, U11A, and U12A. The Q3 has an integrator input which
filters the vertical synch information from the composite synch. The buffers at the input and output of
the integrator gives reliable voltage levels for the vertical synch detector. The U11A triggers on the leading
edge of the detected vertical synch and oneshot timing is set for 14 msec. It acts as noise exclusion
circuit to minimize false vertical triggering. The output of the U11A goes to U12A which fires at the
same time. The output of the U12A goes to the vertical reset circuit, vertical synch generator U19B,
which recreates the 192 usec vertical synch for the RGB connector, and U1A, which creates a 15 line
frame pulse to be used by the color decoder U8.

The vertical reset pulse is generated on the even fields to reset the vertical beam counter of the com-
puter. The field detect circuit consists of U12B, U2B, and U24. U12B generates a 48 usec pulse from
the leading edge of the source horizontal synch, and U2B generates a 16 usec pulse from the leading
edge of the source horizontal synch. By clocking in the detected composite synch into U24A and U24B
DFFs using the trailing edges of the two oneshots and NANDing the outputs of the two DFFs, one can
determine whether the start of the vertical synch is coincident with the beginning of a line or shifted
by half a line. The circuit is configured to detect even fields, and is connected to the vertical reset logic
so that the reset to the computer is sent on the even field. The vertical reset circuit consists of U15A
and U15B. U15B is the field ID FF, and U15A generates a 64 usec pulse immediately after the detected
vertical synch. The start of the pulse is clocked by the output of U17A to meet the setup and hold times
of the vertical reset sample clock of the computer. NAND gate gates the reset pulse during the even field.

GENLOCK SERVICE MANUAL

Theory of Operation (continued)

Color Decoder and Pixel Switch

Once the computer video is synched to the source video, the source video is decoded by the color decoder
U8. U8 is a standard color decoder TDA3301 which has the capability of switching an external RGB
signal over the decoded RGB signal. All of the controls for U8 are preselected with the exception of
hue. The three diodes, CR9, CR10, and CR11, prevents erroneous clamping of the external RGB in-
puts to occur during VCR head switch. The external RGB’s blank level is sampled by U8 during the
color burst interval of the sandcastle signal. When a head switch occurs, the horizontal synch of the
source video jumps by as much as half a line, so that the external RGB blank level is sampled during
the non-blank interval. When a video level is sampled, the clamp circuit does not recover for 3-8 msec
causing blackening on the top half of the picture. The diodes trickle charge the RGB input during the
vertical frame interval. The RGB output of U8 goes to color encoder U21 and three buffers. The three
sets of buffers, Q1-Q2, Q8-Q9, and Q10-Q11, drives 700 mVp-p signal into a 75 ohm load.

Color Encoder

The color encoder U21 takes the RGB outputs of the color decoder and converts it to NTSC composite
signal. The circuit is identical to the encoder circuit on the Amiga computer, except the color burst gating
is done by the encoder which causes color burst to be present during the vertical equalization and synch
periods. The composite output signal is buffered by Q15 to drive 1 Vp-p signal into a 75 ohm load.

Audio Mixer

The audio mixer circuit consists of dual pot R132 and output amplifiers Q17-Q18 and Q19-Q20. The
computer audio inputs are always connected and the circuit gives 0 dB gain when the mixer pot is in
the middle of the range. The source audio inputs have the same gain, but they could be switched on-off
under software control. The source audio control flag is sent out during the blanking periods on the
pixel switch line. The information is sampled on the trailing edge of the vertical frame pulse by U18.
The outputs of U18 then controls the analog switch U22.

GENLOCK SERVICE MANUAL

GENLOCK TROUBLESHOOTING PROCEDURE

The following is a summary of the steps for troubleshooting the Amiga 1300 genlock board. One should
be familiar with the ‘Genlock Theory of Operation’.

The unit should be connected via a 23 wire cable to the Amiga. An external video and audio sources
should normally be connected to the source video and audio inputs.

Each section typically depends on the section that precedes it. If nothing works start from section (0),
if only the audio does not work jump to section (7).

The item within each section usually depends on the item that follows it i.e., if item (b) is okay then
subsequent items (c), (d)... are working. If an item is not okay but the following item is, then the problem
resides with the components associated with the item.

Some sections, like (4), do not have the strict inter-dependent relationship.

Most of the timing on the genlock board are related to the horizontal and vertical timing. Following out-
puts provides convenient scope trigger signal.

Use HSYNCH at pin 16 of U23 to trigger the scope to look at line related signals; the time base should
be set to 10 or 20 uS/div.

Use VSYNCH at pin 5 of U23 to trigger the scope to look at field related signals; the time base should
be set to 2 or 5 mS/div.

Use RGH at pin 2 or 11 of U17 to trigger the scope to look at ramp related signals between pin 2 of
U17 and the drain of Q25; the time base should be set to 10 or 20 uS/div.

Power on check |

First check to see if the computer powers up with the genlock connected.

a. With the mode switch in SOURCE & COMPUTER position, check to see if the Workbench icon is
displayed over the background at power-up.

b. Check the +5, +12, —5 Vdc power supply to the genlock unit.
c. Visually check for missing or wrong component.

VCO and Horizontal Counter (inside the can)

The computer will not run without the 28 MHz oscillator and the horizontal reset signal, so check the
VCO and the beam counter.

a. Check for 15.75 KHz signal at pin 14 of U13; if not check the beam counter U6, U10, U13, and U4.

b. Check for 7 MHz signal at pin 6 of U25; if not check the prescaler U16 and U25.

c. Check for 28 MHz signal at the emitter of Q12; if not check the VCO circuit CR7, Q13, Q12, and
associated components.

Synch Separator and Detector

The genlock depends on the horizontal and vertical timing information which are extracted from the
source composite video.

a. With source video connected, check for external synch detect HIGH level at pin 5 of U1.
b. Check for positive composite synch at pin 9 of U3; if not check the synch separator U3.

c. Check for 5 Vp-p positive composite video at the emitter of Q7; if not check the buffer Q7 and the
amplifier Q16.

GENLOCK SERVICE MANUAL
Troubleshooting Procedure (continued)

Phase Locked Loop

With the cemputer and the synch separator working, the PLL needs to be in lock to synchronize the
computers timing to the source video timing. The Horizontal Timing sheet give the timing relationships
of waveforms when PLL is in lock.

a. With source video disconnected, check TP1 for 4.2 Vdc; if not check pin 7 of U20 for 12 Vdc and
HIGH level of the source synch detector at pin 12 of U1.

b. With the source video reconnected, check for ramp signal at the emitter of Q22; if not check the
ramp generator circuit Q22, U11, and U17.

c. Check for 10 volt strobe signal at the collector of Q21; if not check the strobe generator circuit Q21
and U14.

d. If both the ramp and the strobe signal are present and the PLL is out of lock, check the sample-ana-
hold Q25 and the phase comparator-loop amplifier U20. If the PLL is in lock the pin 2, 3, and 1 of
U20 will be at 2 Vdc.

Synch, Video Decode Timing, and Reset Signals

Once the PLL is locked, timing information is generated from the source video to synchronize the com-
puter, to add synch signal for the composite and RGB video outputs, and to decode the incoming com-
posite video.

a. Check for negative composite synch signal at pin 9 of U23.
b. Check for negative horizontal synch signal at pin 16 of U23; if not check U19 timing.

c. Check for horizontal reset signal at pin 12 of U12; if not check the horizontal reset generator U14
and U17.

d. Check for negative vertical synch signal at pin 5 of U23; if not check U19 timing.
e. Check for 1 mS positive frame pulse at pin 13 of U1.

f. Check for two level sandcastle signal at the collector of Q6; if not check the summing-amplifier Q5
and Q6, then the blanking timer U2 and color burst timer U7.

g. Check for vertical reset signal at pin 3 of U9; if not check the waveforms at the nodes specified on
the Vertical Timing sheet.

Color Decoder and Pixel Switch

Once the incoming video timing information are extracted, they are used to decode the incoming video.

a. With the mode switch in COMPUTER ONLY or SOURCE & COMPUTER mode and peak white image
on the computer, check for 700 mVp-p signal at the collectors of Q2, Q9, and Q11.

b. Check for 1Vp-p signal at the bases of Q2, Q9, and Q11.
c. With the mode switch in the SOURCE & COMPUTER mode, check for the overlayed picture.

d. With the mode switch in SOURCE ONLY mode and with color image on the source video, check
for the color image on the RGB monitor; if not check the crystal Y1 and associated components.

e. To test the clamp bias circuit consisting of CR9, CR10, and CR11, check to see that the picture does
not flicker at top of the screen with VTR as the source video.

Color Encoder

The composite video is generated by the MC1377.

a. With the mode switch in COMPUTER ONLY or SOURCE & COMPUTER mode and peak white image
on the computer, check for 2 Vp-p signal at pin 9 of U21.

b. With the mode switch in SOURCE ONLY mode, check to see that the color of the composite video
out matches the color of the composite video in; if not check for chroma subcarrier at pin 16 of U21.

<)

GENLOCK SERVICE MANUAL

Troubleshooting Procedure (continued)

Audio Circuit and Software Audio Switch

The audio circuit can be checked by connecting an audio source to the computer audio input and see-
ing if the same signal appears at the audio outputs.

a. With source audio bit (AUD) turned on; successively connect audio source to SOURCE AUDIO IN-L

and R, AMIGA AUDIO IN-L and R, and check to see that corresponding audio signal appears on the
AUDIO OUT-L and AUDIO OUT-R outputs.

lf no audio appears when audio is connected to the SOURCE AUDIO IN, check the analog switch
U22, and the switch controller U18.

b. With the source audio bit (AUD) turned off, connect an audio source to SOURCE AUDIO IN-L and
R, and check that no audio comes out of AUDIO OUT-L and R.

w/ Even field

CSYNCH (source)

FIELD !D (reset)

FIELD ID (FF)

V/2 RESET

w/ Odd field

CSYNCH (source)

FIELD |D (reset)

FIELD ID (FF)

V/2 RESET

Relative timing

CSYNCH (source)

CSYNCH (Amiga)

GENLOCK SERVICE MANUAL

VERTICAL TIMING

usxp9 _ | LL tLTILyS TTT? tT otLttitt| | |
U9-P8 a aaa. a, | ae
U15-P8__ (CUTOUT

U9-P3

vero LIL II TTTTIT Iii tl

oea oe

U15-P8

U9-P3

os 5 lines nein

With non-interlaced video source input the V/2 RESET will occur on every field. This applies to both
odd-field only and even-field only video sources.

GENLOCK SERVICE MANUAL

HORIZONTAL TIMING

Source related
| = 64us |
CSYNCH (source) U3-P9 | | | | | |

HSYNCH (detect) U12-P5 a ns es

HSYNCH (output) U23-P16 a Ue

|
| |
| |

SANDCASTLE Q6-C

STROBE (PLL) Q21-C
I

j |
Computer related [| I . |

I!

RGH U13-P14 Oe ee Oe (
| |
|

I :
, I | II !
RAMP (PLL) 7 A a ee
| | | |
H/2 RESET U14-P12 tof 1 by
|

csyncH (Amiga) u-Pt1 [| iis

When the PLL (phase locked loop) is locked the source related horizontal timing and the computer related
horizontal timing will have the timing relationships shown above. If the PLL is our of lock, then the source
related waveforms will continuously shift relative to the computer related waveforms. The horizontal
position control gives slight fixed adjustment between the two set of waveforms when the PLL is locked.

GENLOCK SERVICE MANUAL

TOWER CONNECTOR

JI i” PI

2QMHZ CLKI 1 ern
28MHZ GNDI13
R 3 > SS

G 4 > YS
Bs >see YS

>)
<| xl o
5 | &
~<| <| <
NY = O

ZD 140 eS
GIU 15 =>. Re

NO CONN 8
9
10

TY Yr
INN CIN AN

~v OW WN

9
19
2

2BMHZ CLK
2B8MHZ GND

NO CONN
RIN

GIN

BIN

COMP SYNC
H7ZE RST

23V/2 RST

6 CHROMA CLK
8

10

l2 GND

14

16

1i@ -SV

20 +l2V
22+5V

i

3

IS5NO CONN
17

PIXEL SW

GENLOCK SERVICE MANUAL
PARTS LIST

PCB ASSEMBLY #311500-01

RESISTORS (Continued)

INTEGRATED CIRCUITS

U8 VIDEO DECODER - TDA 390039-01 R122, 146 200 OHM 901550-112
3301 R17, 45,61, | 220 OHM 901550-52
U21 VIDEO ENCODER - MC 1377 390085-01 98, 102, 110
U22 CMOS QUAD SWITCH- CD 901502-01 R72, 75, 86 | 270 OHM 901550-76
4066BE R49 300 OHM 901550-70
U18 CMOS LCD DRIVER - CD 390038-01 R36 330 OHM 901550-14
4054BE R27 360 OHM 901550-108
U20 DUAL OP AMP - MC 1458 390037-01 R10, 32 390 OHM 901550-57
U3 SINGLE COMPARATOR - LM 390040-01 R114 510 OHM 901550-38
710 R26, 71, 74, | 680 OHM 901550-31
U23 OCTAL BUFFER - 74LS244 901521-13 88, 128
2.7, AN, MONOSTABLE NON 901521-76 R29, 34, 35, | 1K OHM 901550-01
12, 14, 19 RETRIG - 74LS221 39, 40, 41,
U6, 10,13 | COUNTER 4 STAGE - 901521-36 68, 73, 83,
74LS161 84, 87, 93,
U1 MONOSTABLE RETRIG - 901521-49 105, 106,
74LS123 108, 109,
U16 D FLIP FLOP - 74874 901525-09 121, 123,
U15, 17, 24 | D FLIP FLOP - 74LS74 901521-06 137, 139,

U4
U25
U5, 9

NAND 8 INPUT - 74LS30
QUAD NAND - 74S00
QUAD NAND - 74LS00

TRANSISTORS

Q25 JUNC FIELD EFFECT - 390214-01 ete
2N4393 !
Q21 SW PNP - 2N5771 390213-01 Jeon eet 901550-23
Q13 RF NPN - 2N5179 390074-01 !
Q1,3,4, | NPN - 2N3904 902658-01 eee ee ee
57.8. 10 R76 3.3K OHM 901550-02
ag R48, 94 3.9K OHM 901550-39
diaes R54, 55, 4.7K OHM 901550-19

22

Q2, 6, 9,
11, 12, 16,
18, 20

S0V-MV2109 12K OHM 901550-11
15K OHM 901550-26
RESISTORS — All are carbon 1/4 watt, 5% unless noted 18K OHM 901550-55

Ri, 101,

160, 166, 27K OHM 901550-15
173, 174 30K OHM 901550-73
R18, 33, 22 OHM 901550-63 47K OHM 901550-22
46, 62 136, 138
R53, 64 33 OHM 901550-105 R95 51K OHM 901550-10
99, 104 R25, 65, 113 | 56K OHM 901550-59
R92, 151 68 OHM 901550-94 68K OHM 901550-35
167, 172 82K OHM 901550-95
R11, 12, 75 OHM 901550-45 100K OHM 901550-07
13, 19, 47 150K OHM 901550-16
63, 97, 135 220K OHM 901550-125
R15, 16, 43,} 100 OHM 901550-49
44, 56, 59, 1.8M OHM 251068-157
750K 901550-87

60, 125, 150

PNP - 2N3906

RECT 10ma 20V-IN4148

VARACTOR 33pF

10 OHM

901521-53
901525-04
901521-01

902707-01

900850-01

390063-01

901550-64

144, 147

1.2K OHM
1.5K OHM

901550-17
901550-69

2K OHM
2.2K OHM

901550-53
901550-18

115, 116,
117, 118,
140, 141,

6.2K OHM 901550-47
6.8K OHM 901550-04
8.2K OHM 901550-05

R20, 38, 91, | 10K OHM

96, 119,

901550-20

22K OHM 901550-12

10

GENLOCK SERVICE MANUAL

PARTS LIST
PCB ASSEMBLY #311500-01

CAPACTIORS (Continued)

CAPACITORS

C45
C59
C55
C27, 26
C28, 43,
56, 70
C64
C104

C18, 38

C23, 41, 94,
95, 105, 106
C3, 29, 32,

36, 37, 50
69, 71, 73,
78, 83, 85,
100
C35

C1, 2, 30,
4, 21, 44,
47, 51, 67,
68, 79, 84,

99, 102, 103,

201, 202
C52

C34

C7, 8,9

10, 11, 12
15, 16, 31,
40, 46, 48,
49, 54, 57,
66, 87, 91

96, 98, 101

VARIABLE 6.8pF-45pF 50V

VARIABLE 4pF-20pF 50V

CER AXL 30pF +5% S50V

CER AXL 22pF NPO=5%
50V

CER AXL 10pF NPO +5%
50V

CER AXL 47pF NPO +5%
50V

CER AXL 51pF NPO +5%
50V

CER AXL 56pF NPO +5%
50V

CER AXL 100pF NPO +5%
50V

CER AXL 180pF NPO +5%
50V

CER AXL 220pF NPO +5%
50V

CER AXL 390pF NPO +5%
50V

CER AXL 470pF NPO +5%
50V

CER AXL 1000pF NPO
+5% 50V

CER AXL 1500pF NPO
+5% 50V

CER AXL .01pF X7R
+10% 50V

CER RAD .015,F COG
+5% 50V

CER RAD .022uF COG
+5% 50V

CER AXL .1F 250
+80 -20% 50V

251029-06
261029-01
900462-24
900462-21
900462-13
900462-29
900462-30
900462-31
900462-37
900462-43
900462-45
900462-51
900462-53

900462-61

900019-01
900019-03
390082-01

C22, 61 CER AXL .15yF X7R +10% 900463-39
50V

C13, 20, 25 | CER AXL .22uF X7R +10% 900463-38
50V

C24, 39 ELECT RAD 1pF +75% -10% 900100-32
25V

C5, 6,62 | ELECT RAD 10uF +75% -10% 900100-01

74, 75, 76 25V

77, 81, 82,

88, 89, 90,

93

C92 TANT RAD 10pF +20% 10V 900402-01

C42, 53,58 | ELECT RAD 22uF +20% 16V —«-:251894-24

C14, 80 ELECT RAD 47pF +20% 50V —=«-:25 1894-65

C19 ELECT RAD 100uF +20% 25V —-:251894-39

MISCELLANEOUS

RELAY 4 PDT PCB MT 5V

SWITCH TOGGLE SP-3 POS
PCB MT

CONNECTOR D SUB 23
PIN MALE

CONNECTOR CARD EDGE DUAL

12 POS .1CTR
SHIELD FENCE
SHIELD TOP
CONNECTOR, PHONO JACK
CONNECTOR, PHONO JACK
CONNECTOR, PHONO JACK
DELAY LINE 400ns
TRANSFORMER CHROMA
FILTER
FERRITE BEAD
INDUCTOR 3.3 nH + 10%
Q=45 MIN
INDUCTOR 1.2 nH +10%
Q=25 MIN
INDUCTOR 33 pH +10%
Q=85 MIN
POTENTIOMETER DUAL
LIN 10K +20%
POTENTIOMETER LIN 10K
+20%
POTENTIOMETER 10K
POTENTIOMETER TRIM 10K

390094-01
390212-01

327032-01
390033-01
327044-01
327323-01
327324-01
327324-02
327324-03
252124-01
252123-01

903025-02
901151-19

901151-14
390041-01
390034-01
390035-01

390035-02
902267-10

11

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13

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Computer Systems Division
1200 Wilson Drive
West Chester, PA 19380

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